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Order Management Process Steward (Day 2.1)
Santa Clara, CA
INTEL
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TMGF Forecast to Stock Process Steward
Santa Clara, CA
INTEL
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Senior Hardware Development Engineer, AWS Server Engineering
Cupertino, CA
Amazon Data Services, Inc.
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Lead
UX Product
Designer
- Remote/Hybrid CA
San Francisco, CA
Liberty Mutual
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Chief Kubernetes Architect
San Jose, CA
NetApp
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Principal CPU Architect, Fabric Congestion and QOS Management
Santa Clara, CA
NVIDIA
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Medical Director, Oncology Clinical Development
San Francisco, CA, San Jose, CA, Oakland, CA
Jazz Pharmaceuticals
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Sr. Analog
Design
Lead
San Jose, CA
Micron Technology
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Physical
Design
Lead
San Bruno, CA
CareerBuilder
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GPU
Design
Lead
Santa Clara, CA
CareerBuilder
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RTL
Design
Lead
San Jose, CA
Advanced Micro Devices , Inc.
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Analog
Design
Lead
- Power Management
Cupertino, CA
CareerBuilder
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Analog
Design
Lead
- Power Management
Cupertino, CA
Apple
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Physical
Design
Lead
- Custom Silicon Management
Cupertino, CA
CareerBuilder
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Debug/Trace/Monitoring RTL
Design
Lead
Santa Clara, CA
SiFive
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Systems Test
Design
Lead
Cupertino, CA
Apple
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RTL
Design
Lead
San Jose, CA
CareerBuilder
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SoC
Design
Lead
Santa Clara, CA
Intel
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